ppg3 3f doc #97010 data delay devices, inc. 1 1/15/97 3 mt. prospect ave. clifton, nj 07013 3-bit programmable pulse generator (series ppg33f) features packages digitally programmable in 7 steps monotonic pulse-width-vs-address variation rising edge triggered two separate outputs: inverting & non-inverting precise and stable pulse width input & outputs fully ttl interfaced & buffered 10 t 2 l fan-out capability fits standard 14-pin dip socket auto- insertable functional description the ppg33f-series device is a 3-bit digitally programmable pulse generator. the width, pw a , depends on the address code (a2-a0) according to the following formula: pw a = pw 0 + t inc * a where a is the address code, t inc is the incremental pulse width of the device, and pw 0 is the inherent pulse width of the device. the incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. reset is held low during normal operation. when it is brought high, out and out/ are forced into low and high states, respectively, and the unit is ready for the next trigger input. the address is not latched and must remain asserted while the output pulse is active. series specifications programmed pulse width tolerance: 5% or 1ns, whichever is greater inherent width (pw 0 ): 9ns typical inherent delay (t to ): 3.5ns 2ns operating temperature: 0 to 70 c supply voltage v cc : 5vdc 5% supply current: i cc = 41ma typical 1997 data delay devices data delay devices, inc. 3 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 trig out n/c n/c n/c n/c res gnd vcc out/ n/c n/c n/c a0 a1 a2 14 13 12 11 10 9 8 1 2 3 4 5 6 7 trig out n/c n/c n/c res gnd vcc out/ n/c n/c a0 a1 a2 dip ppg33f-xx commercial ppg33f-xxm military gull-wing ppg33f-xxc3 commercial ppg33f-xxmc3 military pin descriptions trig trigger input out non-inverted output out/ inverted output a0-a2 address bits res reset vcc +5 volts gnd ground dash number specifications part number incremental width per step ( ns) total width change ( ns) ppg33f-.5 0.5 0.3 3.50 1.00 ppg33f-1 1 0.4 7.00 1.00 ppg33f-2 2 0.4 14.0 1.00 ppg33f-3 3 0.5 21.0 1.05 ppg33f-4 4 0.5 28.0 1.40 ppg33f-5 5 0.6 35.0 1.75 ppg33f-6 6 0.7 42.0 2.10 ppg33f-8 8 0.8 56.0 2.80 ppg33f-10 10 1.0 70.0 3.50 ppg33f-20 20 1.5 140 7.00 ppg33f-30 30 1.8 210 10.5 ppg33f-40 40 2.0 280 14.0 ppg33f-50 50 2.5 350 17.5 note: any das h number between .5 and 50 not shown is also available.
ppg33f doc #97010 data delay devices, inc. 2 1/15/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com application notes device timing the timing definitions and restrictions for the ppg33f are shown in figure 1. the unit is activated by a rising edge on the trig input. after a time, t to (called the inherent delay), the rising edge of the pulse appears at out. the duration of the pulse is given by the above equation. for the duration of the pulse, the device ignores subsequent triggers. once the falling edge of the pulse has appeared at out, an additional time, t otr , is required before the device can respond to the next trigger. at power-up, the state of the ppg33f is unknown. consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, pw t . after this time, the unit will function properly. if your application requires that the device function immediately, issue a quick reset at power-up. power supply bypassing the ppg33f relies on a stable power supply to produce repeatable pulses within the stated tolerances. a 0.1uf capacitor from vcc to gnd, located as close as possible to each vcc pin, is recommended. a wide vcc trace should connect all vcc pins externally, and a clean ground plane should be used. increment tolerances please note that the increment tolerances listed represent a design goal. although most increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. monotonicity is, however, guaranteed over all addresses. ` t oax t rts t tw t to pw a a2-a0 res trig out out/ figure 1: timing diagram a i a i+1 t skew t ats t ro t otr t tw t rw
ppg3 3f doc #97010 data delay devices, inc. 3 1/15/97 3 mt. prospect ave. clifton, nj 07013 device specifications table 1: ac characteristics parameter symbol min typ max units total programmable pulse width pw t 7 t inc inherent pulse width pw 0 6.0 9.0 12.0 ns trigger to output delay t to 1.5 3.5 5.5 ns reset to output delay t ro 17.0 ns output skew t skew 1.5 ns trigger pulse width t tw 5.0 ns reset pulse width t rw 10.0 ns reset to trigger setup time t rts 9.0 ns address to trigger setup time t ats 6.0 ns output low to address change t oax 0.0 ns output to trigger recovery time t otr 15 % of pw t * *or 10ns, whichever is greater table 2: absolute maximum ratings parameter symbol min max units notes dc supply voltage v cc -0.3 7.0 v input pin voltage v in -0.3 v dd +0.3 v storage temperature t strg -55 150 c lead temperature t lead 300 c 10 sec table 3: dc electrical characteristics (0c to 70c, 4.75v to 5.25v) parameter symbol min typ max units notes high level output voltage v oh 2.5 3.4 v v cc = min, i oh = max v ih = min, v il = max low level output voltage v ol 0.35 0.5 v v cc = min, i ol = max v ih = min, v il = max high level output current i oh -1.0 ma low level output current i ol 20.0 ma high level input voltage v ih 2.0 v low level input voltage v il 0.8 v input clamp voltage v ik -1.2 v v cc = min, i i = i ik input current at maximum input voltage i ihh 0.1 ma v cc = max, v i = 7.0v high level input current i ih 20 m a v cc = max, v i = 2.7v low level input current i il -0.6 ma v cc = max, v i = 0.5v short-circuit output current i os -60 -150 ma v cc = max output high fan-out 25 unit output low fan-out 12.5 load
ppg33f doc #97010 data delay devices, inc. 4 1/15/97 tel: 973-773-2299 fax: 973-773-9672 http://www.datadelay.com package dimensions .195 .010 .830 max. 1 2 3 4 5 6 7 8 .290 max. .020 typ. .440 max. .300 typ. .010 typ. .600 typ. .030 .005 9 10 11 12 13 14 dip (ppg33f-xx, ppg33f-xxm) .880 .020 .882 .005 .020 typ. .040 typ. .100 .090 .700 .280 max. .590 max. .010 .002 .050 .010 .710 .005 .007 .005 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 gull-wing (ppg33f-xxc3, ppg33f-xxmc3)
ppg3 3f doc #97010 data delay devices, inc. 5 1/15/97 3 mt. prospect ave. clifton, nj 07013 delay line automated testing test conditions input: output: ambient temperature: 25 o c 3 o c load: 1 fast-ttl gate supply voltage ( vcc): 5.0v 0.1v c load : 5pf 10% input pulse: high = 3.0v 0.1v threshold: 1.5v (rising & falling) low = 0.0v 0.1v source impedance: 50 w max. rise/fall time: 3.0 ns max. (measured between 0.6v and 2.4v ) pulse width: pw in = 10ns period: per in = 2 x max. pulse width note: the above conditions are for test only and do not in any way restrict the operation of the device. out out trig in ref trig test setup device under test (dut) time interval counter pulse generator computer system printer in timing diagram for testing t to pw a per in pw in t rise t fall 0.6v 0.6v 1.5v 1.5v 2.4v 2.4v 1.5v 1.5v v ih v il v oh v ol input signal output signal
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